Maxim-Integrated /max32650 /HPB /MCR[1]

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MCR[1]

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (hyperFlash)DEV_TYPE 0 (mem_space)CRT 0 (variable)READ_LATENCY 0 (dis)HSE 0MAXLEN0 (dis)MAXLEN_EN

MAXLEN_EN=dis, READ_LATENCY=variable, DEV_TYPE=hyperFlash, CRT=mem_space, HSE=dis

Description

HPB Memory Configuration Register.

Fields

DEV_TYPE

Memory device type select.

0 (hyperFlash): HyperFlash.

1 (xccelaPSRAM): Xccela PSRAM.

2 (hyperRAM): HyperRAM.

CRT

Configuration register target select.

0 (mem_space): Access memory space.

1 (config_reg_space): Access configuration register space.

READ_LATENCY

Xccela fixed read latency enable.

0 (variable): Variable read latency.

1 (fixed): Fixed read latency.

HSE

Xccela half sleep exit.

0 (dis): Half-Sleep exit disabled.

1 (en): Half-Sleep exit enabled.

MAXLEN

Maximum read/write…

MAXLEN_EN

Maximum CS# length enable.

0 (dis): Configurable CS# low time disabled.

1 (en): Configurable CS# low time enabled.

Links

()